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Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
FEATURES
* Fully integrated PLL * 17 LVCMOS/LVTTL outputs, 15 typical output impedance * Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK * Maximum output frequency: 166.67MHz * Maximum crystal input frequency: 38MHz * Maximum REF_CLK input frequency: 83.33MHz * Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz simultaneously * Separate feedback control for generating PCI / PCI-X frequencies from a 20MHz or 25MHz crystal or 33.333MHz or 66.666MHz reference frequency * Cycle-to-cycle jitter: 70ps (maximum) * Period jitter, RMS: 17ps (maximum) * Output skew: 230ps (maximum) * Bank skew: 40ps (maximum) * Static phase offset: 0 150ps (maximum)
GENERAL DESCRIPTION
The ICS8761 is a low voltage, low skew PCI / PCI-X Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8761 has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The ICS8761 has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay". Using a 20MHz or 25MHz crystal or a 33.333MHz or 66.666MHz reference frequency, the ICS8761 will generate output frequencies of 33.333MHz, 66.666MHz, 100MHz and 133.333MHz simultaneously.
ICS
The low impedance LVCMOS/LVTTL outputs of the ICS8761 are designed to drive 50 series or parallel terminated transmission lines.
BLOCK DIAGRAM
OEA MR D_SELA0 D_SELA1 REF_CLK XTAL1
OSC
1 0
/3 /4 /6 /12
00 01 10 11
* Full 3.3V or 3.3V core, 2.5V multiple output supply modes * 0C to 85C ambient operating temperature * Lead-Free package available
QA0 QA1
0 1
PIN ASSIGNMENT
VDDOC VDDOC VDDOD VDDOD GND GND GND GND QC0 QC1 QC2 QC3 QD0 QD1 QD2
QA3
REF_CLK 1 2 3 4 5 6 7 8 9
XTAL2 XTAL_SEL FB_IN PLL_SEL OEB D_SELB1 D_SELB0
PLL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
QD3
QA2
GND FB_OUT VDDOFB FB_IN VDD FBDIV_SEL0 FBDIV_SEL1 MR VDD D_SELD0 D_SELD1 OED OEB D_SELB0 D_SELB1 GND
00 01 10 11
QB0 QB1 QB2 QB3
GND XTAL1 XTAL2 VDD XTAL_SEL PLL_SEL VDDA VDD
QC0
OEC
00 01 10 11
QC1
ICS8761
41 40 39 38 37 36 35 34
D_SELC1 D_SELC0 OED
00 01 10 11
QC2 D_SELC0 QC3 D_SELC1
OEC OEA D_SELA0 D_SELA1 GND
10 11 12 13 14 15
QD0 QD1 QD2 QD3
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
QA0 QA1 QA2 QA3 QB0 QB1 QB2 VDDOA VDDOA VDDOB VDDOB GND GND GND GND QB3
D_SELD1 D_SELD0
/6 /12 /16 /20
00 01 10 11
FB_OUT
FBDIV_SEL1 FBDIV_SEL0
8761CY
64-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
Type Input Power Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 16, 17, 21, 25, 29, 33, 48, 52, 56, 60, 64 3, 4 5, 9, 40, 44 6 7 8 10, 11 12 13 14, 15 18, 20, 22, 24 19, 23 26, 28, 30, 32 27, 31 34, 35 36 37 38, 39 Name REF_CLK GND XTAL1, XTAL2 VDD XTAL_SEL PLL_SEL VDDA D_SELC0, D_SELC1 OEC OEA D_SELA0, D_SELA1 QA0, QA1, QA2, QA3 VDDOA QB0, QB1, QB2, QB3 VDDOB D_SELB1, D_SELB0 OEB OED D_SELD1, D_SELD0 MR
Pulldown Reference clock input. LVCMOS / LVTTL interface levels. Power supply ground.
Input Power Input Input Power Input Input Input Input Output Power Output Power Input Input Input Input Pulldown Pullup Pullup Pulldown Pulldown Pullup Pullup Pulldown Pullup Pullup
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Core supply pins. Selects between crystal oscillator or reference clock as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW. LVCMOS / LVTTL interface levels. Selects between PLL and bypass mode. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels. Analog supply pin. See Applications Note for filtering. Selects divide value for Bank C outputs as described in Table 3. LVCMOS / LVTTL interface levels. Determines state of Bank C outputs. When HIGH, outputs are enabled. When LOW, outputs are disabled. LVCMOS / LVTTL interface levels. Determines state of Bank A outputs. When HIGH, outputs are enabled. When LOW, outputs are disabled. LVCMOS / LVTTL interface levels. Selects divider value for Bank A outputs as described in Table 3. LVCMOS / LVTTL interface levels. Bank A clock outputs. 15 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank A outputs. Bank B clock outputs. 15 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank B outputs. Selects divider value for Bank B outputs as described in Table 3. LVCMOS / LVTTL interface levels. Determines state of Bank B outputs. When HIGH, outputs are enabled. When LOW, outputs are disabled. LVCMOS / LVTTL interface levels. Determines state of Bank D outputs. When HIGH, outputs are enabled. When LOW, outputs are disabled. LVCMOS / LVTTL interface levels. Selects divider value for Bank D outputs as described in Table 3. LVCMOS / LVTTL interface levels. Active HIGH Master reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects divider value for bank feedback output as described in Table 3. LVCMOS / LVTTL interface levels. Selects divider value for bank feedback output as described in Table 3. LVCMOS / LVTTL interface levels. Feedback input to phase detector for generating clocks with "zero delay". LVCMOS / LVTTL interface levels.
41
Input
Pulldown
42 43 45
FBDIV_SEL1 FBDIV_SEL0 FB_IN
Input Input Input
Pulldown Pullup Pulldown
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
Type Power Output Output Power Output Power Description Output supply pin for FB_Out output. Feedback output. Connect to FB_IN. 15 typical output impedance. LVCMOS / LVTTL interface levels. Bank D clock outputs. 15 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank D outputs. Bank C clock outputs. 15 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank C outputs.
Number 46 47 49, 51, 53, 55 50, 54 57, 59, 61, 63 58, 62
Name VDDOFB FB_OUT QD3, QD2, QD1, QD0 VDDOD QC3, QC2, QC1, QC0 VDDOC
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE 1 Output Impedance VDD, VDDA = 3.465V; VDDOx = 3.465V VDD, VDDA = 3.465V; VDDOx = 2.625V 15 Test Conditions Minimum Typical Maximum 4 51 51 9 11 Units pF K K pF pF
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, VDDOFB.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs MR 1 0 X OEA 1 1 0 OEB 1 1 0 OEC 1 1 0 OED 1 1 0 QA0:QA3 LOW Active HiZ LOW Active HiZ Outputs QB0:QB3 QC0:QC3 LOW Active HiZ QD0:QD3 LOW Active HiZ
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL 0 1 Operating Mode Bypass PLL
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs XTAL_SEL 0 1 PLL Input REF_CLK XTAL Oscillator
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
TABLE 3D. CONTROL FUNCTION TABLE
Inputs Reference Frequency Range (MHz) 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25 12.5 - 25 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25 12.5 - 25 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25 12.5 - 25 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
Outputs PLL_SEL =1 QX0:QX3 x2 x4 x 5.33 x 6.67 x 1.5 x3 x4 x5 x1 x2 x 2.67 x 3.33 /2 /1 x 1.33 Frequency QX0:QX3 (MHz) 83.33 - 166.67 83.33 - 166.67 83.33 - 166.67 83.33 - 166.67 62.4 - 125 62.4 - 125 62.4 - 125 62.4 - 125 41.6 - 83.33 41.6 - 83.33 41.6 - 83.33 41.6 - 83.33 20.8 - 41.67 20.8 - 41.67 20.8 - 41.67 FB_OUT (MHz) 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25 12.5 - 25 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25 12.5 - 25 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25 12.5 - 25 41.6 - 83.33 20.83 - 41.67 15.62 - 31.25
D_SELx1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
D_SELx0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
FBDIV_SEL1 FBDIV_SEL0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1 1 1 1 12.5 - 25 x 1.67 20.8 - 41.67 12.5 - 25 NOTE: D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0, D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
TABLE 3E. CONTROL FUNCTION TABLE (PCI CONFIGURATION)
Inputs D_SELx1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 D_SELx0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 FBDIV_SEL1 FBDIV_SEL0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Reference Frequency (MHz) 66.67 33.33 25 20 66.67 33.33 25 20 66.67 33.33 25 20 66.67 33.33 25 Outputs PLL_SEL = 1 QX0:QX3 x2 x4 x 5.33 x 6.67 x 1.5 x3 x4 x5 x1 x2 x 2.67 x 3.33 /2 /1 x 1.33 Frequency QX0:QX3 FB_OUT (MHz) (MHz) 133 66.67 133 133 133 100 100 100 100 66.67 66.67 66.67 66.67 33.33 33.33 33.33 33.33 25 20 66.67 33.33 25 20 66.67 33.33 25 20 66.67 33.33 25
1 1 1 1 20 x 1.67 33.33 20 NOTE: D_SELx1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELx0 denotes D_SELA0, D_SELB0, D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDOx + 0.5V 41.1C/W (0 lfpm) -65C to 150C
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = 0C TO 85C
Symbol VDD VDDA VDDOx IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 175 55 25 Units V V V mA mA mA
Output Supply Current; NOTE 2 IDDOx NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB. NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = 0C TO 85C
Symbol Parameter OEA:OED, XTAL_SEL, MR, D_SELA0:D_SELD0, FB_IN, Input D_SELA1:D_SELD1, PLL_SEL, High Voltage FBDIV_SEL0, FBDIV_SEL1 REF_CLK OEA:OED, XTAL_SEL, MR, D_SELA0:D_SELD0, FB_IN, Input Low Voltage D_SELA1, D_SELD1, PLL_SEL REF_CLK D_SELA0:D_SELD0, FB_IN, MR, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 High Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED D_SELA0:D_SELD0, FB_IN, MR, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 Low Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low -5 5 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 2.6 0.5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V A A
VIH
VIL
IIH
IIL
VOH VOL IOZL
IOZH Output Tristate Current High NOTE 1: Outputs terminated with 50 to VDDOx/2. See Parameter Measurement Information section, "3.3V Output Load Test Circuit".
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
Test Conditions f = 50MHz Minimum -150 Typical Maximum 166.67 150 40 230 f = 50MHz; NOTE 4, 7 f = 25MHz XTAL, 133.3MHz out 70 190 17 1 20% to 80% 20% to 80% 300 300 800 800 Units MHz ps ps ps ps ps ps ms ps ps %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = 0C TO 85C
Symbol fMAX t(O) Parameter Output Frequency Static Phase Offset; NOTE 1, 7 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Cycle-to-Cycle Jitter; 6 Period Jitter, RMS; NOTE 4, 6, 7, 8 PLL Lock Time Output Rise Time Output Fall Time
t sk(b) t sk(o) tjit(cc) tjit(per)
tL tR tF
odc Output Duty Cycle; NOTE 5, 7 45 55 NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. Measured from VDD/2 of the input to VDDOx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOx/2. NOTE 4: Jitter performance using LVCMOS inputs. NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6). NOTE 8: This parameter is defined as an RMS value.
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 3.465 2.625 160 50 210 Units V V V mA mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDOX = 2.5V5%, TA = 0C TO 85C
Symbol VDD VDDA VDDOx IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Analog Supply Current
Output Supply Current; NOTE 2 IDDOx NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB. NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB.
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDOX = 2.5V5%, TA = 0C TO 85C
Symbol Parameter OEA:OED, XTAL_SEL, MR, D_SELA0:D_SELD0, FB_IN, Input D_SELA1:D_SELD1, PLL_SEL, High Voltage FBDIV_SEL0, FBDIV_SEL1 REF_CLK OEA:OED, XTAL_SEL, MR, D_SELA0:D_SELD0, FB_IN, Input D_SELA1:D_SELD1, PLL_SEL, Low Voltage FBDIV_SEL0, FBDIV_SEL1 REF_CLK D_SELA0:D_SELD0, FB_IN, MR, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 High Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED D_SELA0:D_SELD0, FB_IN, MR, D_SELA1:D_SELD1, REF_CLK, Input FBDIV_SEL1 Low Current XTAL_SEL, PLL_SEL, FBDIV_SEL0, OEA:OED Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low -5 5 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.8 0.5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V A A
VIH
VIL
IIH
IIL
VOH VOL IOZL
IOZH Output Tristate Current High NOTE 1: Outputs terminated with 50 to VDDOx/2. See Parameter Measurement Information section, "3.3V/2.5V Output Load Test Circuit".
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
Test Conditions f = 50MHz Minimum -350 Typical Maximum 166.67 20 40 230 f = 50MHz; NOTE 4, 7 f = 25MHz XTAL, 133.3MHz out 70 190 17 1 20% to 80% 20% to 80% 300 300 800 800 Units MHz ps ps ps ps ps ps ms ps ps %
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDOX = 2.5V5%, TA = 0C TO 85C
Symbol fMAX t(O) Parameter Output Frequency Static Phase Offset; NOTE 1, 7 Bank Skew; NOTE 2, 6 Output Skew; NOTE 3, 6 Cycle-to-Cycle Jitter; NOTE 6 Period Jitter, RMS; NOTE 4, 6, 7, 8 PLL Lock Time Output Rise Time Output Fall Time
t sk(b) t sk(o) tjit(cc) tjit(per)
tL tR tF
odc Output Duty Cycle; NOTE 5, 7 45 55 NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. Measured from VDD/2 of the input to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOx/2. NOTE 4: Jitter performance using LVCMOS inputs. NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6). NOTE 8: This parameter is defined as an RMS value
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 7 10 Test Conditions Minimum Typical Maximum 38 70 Units MHz pF Fundamental
TABLE 7. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V5%, TA = 0C TO 85C
Symbol fREF Parameter Reference Frequency Test Conditions Minimum 10 Typical Maximum 83.33 Units MHz
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDA, VDDOx
SCOPE
Qx
VDD, VDDA
SCOPE
VDDOx
GND
Qx
LVCMOS
GND
LVCMOS
-1.165V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DDOX
Qx
2
Qx
VDDO 2
V
DDOX
Qy
2 tsk(o)
Qy
tsk(o)
VDDO 2
OUTPUT SKEW
BANK SKEW (Where X denotes outputs in the same Bank)
V
DDOX
V
DDOX
V
DDOX
VDD
tcycle
n
t(O)
1000 Cycles
CYCLE-TO-CYCLE JITTER
VDDOX 2 t PW t PERIOD
STATIC PHASE OFFSET
VDDOX
VDDOX 2
QAx, QBx, QCx, QDx, FB_OUT
2
20% Clock Outputs t
R
odc =
t PW t PERIOD
tPW & tPERIOD
8761CY
OUTPUT RISE/FALL TIME
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REV. C SEPTEMBER 7, 2004
tjit(cc) = tcycle n -tcycle n+1
QAx, QBx, QCx, QDx
2
2
2
REF_CL:K
2
tcycle n+1
FB_IN
VDD 2
80%
80%
20% t
F
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8761 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F VDDA .01F 10 F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8761 crystal interface is shown in Figure 2. While layout the PC Board, it is recommended to provide C1 and C2 spare footprints for frequency fine tuning. For an 18pF parallel resonant crystal, the C1 and C2 are expected to be ~10pF and ~5pF respectively.
XTAL2
C1 SPARE
X1 18pF Parallel Cry stal
XTAL1
C2 SPARE
FIGURE 2. CRYSTAL INPUT INTERFACE
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
near the power pin. For ICS8761, the unused clock outputs can be left floating. The optional C1 and C2 are spare footprints for frequency fine tuning.
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8761. In this example, the input is driven by an ICS HiPerClockS LVHSTL driver. The decoupling capacitors should be physically located
Zo = 50
R1 36
VDDO
VDD
Zo = 50
R2
Receiv er
GND QC0 VDDOC QC1 GND QC2 VDDOC QC3 GND QD0 VDDOD QD1 GND QD2 VDDOD QD3
C1 SP
1K
1K
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
R5
R6
U1
36
Receiv er
VDD
X1 25MHz,18pF
R7 10
C2 SP
VDD
C17 0.1u
C16 10u
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
REF_CLK GND XTAL1 XTAL2 VDD XTAL_SEL PLL_SEL VDDA VDD D_SELC0 D_SELC1 OEC OEA D_SELA0 D_SELA1 GND
GND FB_OUT VDDOFB FB_IN VDD FBDIV_SEL0 FBDIV_SEL1 MR VDD D_SELD0 D_SELD1 OED OEB D_SELB0 D_SELB1 GND
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDDO
VDD
Zo = 50
R3 36
Receiv er
SP = Spare, Not Install
ICS8761
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDO
GND QA0 VDDOA QA1 GND QA2 VDDOA QA3 GND QB0 VDDOB QB1 GND QB2 VDDOB QB3
Zo = 50
R4
Logic Input Pin Examples
(U1,5)
VDD
(U1,9)
(U1,40)
(U1,44)
36
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 SP
VDD
C6 0.1u
C5 0.1u
C4 0.1u
C3 0.1u
VDD=3.3V
VDDO=3.3V
Receiv er
To Logic Input pins
RD1 SP
RD2 1K
To Logic Input pins
(U1,23) (U1,19) VDDO
C7 0.1u
(U1,27)
(U1,31)
(U1,50)
(U1,54)
(U1,58)
(U1,62)
(U1,46)
C8 0.1u
C9 0.1u
C10 0.1u
C11 0.1u
C12 0.1u
C13 0.1u
C14 0.1u
C15 0.1u
FIGURE 3. ICS8761 CLOCK GENERATOR SCHEMATIC EXAMPLE
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
64 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.8C/W 41.1C/W
200
48.5C/W 35.8C/W
500
43.2C/W 33.6C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8761 is: 6040
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
64 LEAD TSSOP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BCD MINIMUM NOMINAL 64 --1.40 --12.00 BASIC 10.00 BASIC 7.50 Ref. 12.00 BASIC 10.00 BASIC 7.50 Ref. 0.50 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
Marking ICS8761CY ICS8761CY ICS8761CYLN ICS8761CYLN ICS8761CYLF ICS8761CYLF Package 64 Lead LQFP 64 Lead LQFP on Tape and Reel 64 Lead "Lead-Free/Annealed" LQFP 64 Lead "Lead-Free/Annealed" LQFP on Tape and Reel 64 Lead "Lead-Free" LQFP 64 Lead "Lead-Free" LQFP on Tape and Reel Count 160 per tray 500 160 per tray 500 160 per tray 500 Temperature 0C to 85C 0C to 85C 0C to 85C 0C to 85C 0C to 85C 0C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8761CY ICS8761CYT ICS8761CYLN ICS8761CYLNT ICS8761CYLF ICS8761CYLFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8761CY
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REV. C SEPTEMBER 7, 2004
Integrated Circuit Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Pin Description Table, revised Master Reset description. Pin Description Table, pin 43 should be labeled at a PULL-UP instead of a PULL-DOWN. LVCMOS DC Characteristics table -in the IIH and IIL rows, FBDIV_SEL0 was deleted from the "pulldown" row and was added to the "pullup" row. Features section, changed max. output frequency from 200MHz to 183.3MHz, and max. REF_CLK input frequency from 100MHz to 91.6MHz. Control Function Table - revised Reference Frequency Range column and Frequency columns to reflect the output frequency change. AC Characteristics tables - changed Output Frequency from 200MHz max. to 183.3MHz max. Pin Description Table, revised cr ystal description. AC Characteristics tables - changed Period Jitter measurement to Period Jitter, RMS and added NOTE 8. Added Cr ystal information. Added Schematic Example in the Application Information Section. Pin Description Table - revised MR description. Power Supply Tables - changed VDD parameter to read "Core Supply Voltage" from "Positive Supply Voltage". Deleted Cr ystal Input Interface section. Updated Schematic Example diagram. Updated Features to reflect T5A 3.3V AC Characteristics (see below). Adjusted Ref. Frequency Range and Frequency columns. Changed IDD max. from 150mA to 175mA, IDDA max. from 50mA to 55mA, and IDDO max. from 330mA to 25mA. Changed fMAX from 183.3MHz max. to 166.67MHz max. Changed RMS tjit(per) from 20ps max. to 17ps max. Features Section - added Lead-Free bullet. Added Cr ystal Section. Ordering Information Table - added Lead-Free/Annealed Par t Number. Ordering Information Table - added Lead-Free Par t Number. 4/10/03 1/20/03 Date 8/15/02 11/05/02
Rev A A
Table T1 T1 T4B, T4D
Page 2 2 6, 8 1
B
T3D T5A, T5B T1 T5A, T5B
4 7, 9 2 7, 9 10
11/06/02
B 11 2 5, 7 10 10 1 T3D C T4A T5A & T5B 4 5 6&8 1 10 14 14
T1 T4A, T4C B
3/25/03
C C
8/2/04 8/7/04
8761CY
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REV. C SEPTEMBER 7, 2004

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